1. Field of the Invention
The present invention relates to a reading circuit for a semiconductor memory such as a dynamic random access memory (referred to as "DRAM" hereinafter) and a static random access memory (referred to as "SRAM" hereinafter), and in particular to a technique of a reading circuit effective to a semiconductor memory incorporating, for example, a sensing system for clamping a potential difference between a data pair read out of a memory cell.
2. Description of the Prior Art
The following describes a conventional reading circuit for a semiconductor memory with reference to FIGS. 14 through 16.
FIG. 14 shows a reading circuit for an SRAM incorporating a clamping system for clamping a potential difference between a bit line pair 3, FIG. 15 explains the operation of the reading circuit, and FIGS. 16(a) and 16(b) show typical memory cells 5 of SRAMs, where FIG. 16(a) depicts a memory cell 5 of a resistor load type, and FIG. 16(b) a memory cell of a complementary metal oxide semiconductor (referred to as "CMOS" hereinafter) type. Connecting relations between complementary bit lines BL, /BL (3), a word line WL (9), and the memory cell 5 are as shown in FIGS. 16(a) and 16(b).
Now the reading circuit shown in FIG. 14 is described in conjunction with the operation explanatory view of FIG. 15. An equalizer circuit made up of first, second, and third transistors 2a, 2b, and 2c serves to precharge and equalize a bit line pair 3 with respect to a supply voltage of a first power source 20 using an equalizing signal ATD fed via a first control line 6, obtained by inverting a transition detection signal LTD (indicated by a broken line in FIG. 15) for detecting transition of a column address 17 or a row address 16. The equalizer circuit made up of the transistors 2a, 2b, and 2c is controlled by a second control signal FF fed through a second control line (18) which represents an OR relation between a delay signal OFQ on a delay line (7) obtained from the transition detection signal LTD and a discrimination signal CEWE fed through a signal line (8) for discriminating whether a write cycle or a read cycle is in operation. The data stored in the memory cell 5 is read out to the bit line pair 3 by turning on the word line 9.
Meanwhile, a clamping circuit made up of fourth and fifth transistors 1a and 1b is turned off so as to release the clamping of the bit line pair 3 for a duration of a period from t=t0 to t=t1 upon completion of the equalizing operation effected by the equalizer circuit (2a, 2b and 2c). By this arrangement, the clamping operation of the clamping circuit (1a, 1b) can be prevented in a period when the data signal read out of the memory cell 5 to the bit line pair 3 is not enough large.
The potential difference during the release of the clamping by turning off the clamping circuit is further transferred to the subsequent stage, which is effected by connecting the bit line pair 3 to the input of a differential amplifier 4 through a sub-bit line pair SBL and /SBL (30) in the subsequent stage by feeding a third control signal CD decoded by the column address 17 via a third control line (13). The potential difference between a data line pair 14 is amplified by turning-on the differential amplifier 4 by feeding a fourth control signal SE via a fourth control line 10. Subsequently, the signal of the amplified potential difference is further amplified by plural-stage amplifiers 4 to be finally output through an output buffer 11.
It is noted here that a write operation is performed using a write bus 15, which goes a high-impedance state in a read operation and which outputs write data in a write operation. In a write operation, the discrimination signal CEWE on the signal line (8) goes high so that the clamping signal FF on the second control line (18) also goes high, causing the clamping operation to be released in a D.C. manner. Since the writing circuit is not so related to the circuit of the present invention, its detailed description is omitted here.
As a background of introducing the conventional technique in the field, high integration of SRAMs has involved an increasing number of memory cells 5 to be connected to the bit line pair 3 s that the floating capacity of the bit line pair 3 would drastically increase, resulting in that the equalizing operation takes much time to perform a read operation. Therefore, the delay time for reading operation will increase. By this reason, the technique has been introduced with a view of reducing the delay time for the equalizing operation by suppressing the amplitude of the data signal on the bit line 3, that is, by clamping the potential difference between the bit line pair 3.
However, the clamping operation, as stated above, is carried out in such a manner that the amplitude of the potential difference between the bit line pair 3 is suppressed by making a current flow in DC through the bit line 3 using the clamping circuit consisting of the transistors 1a and 1b. Therefore, immediately after the voltage data of the memory cell 5 is read out to the bit line pair 3 by turning on the level of the word line 9, the read-out voltage data on the bit line pair 3 disadvantageously results in a small one due to the effect of the clamping operation.
Therefore, in a conventional method as shown in FIGS. 14 to 16, there has been proposed as a solution of the problem in the Reference Literature 1 (Miyaji et al. "A 25 ns 4Mb CMOS SRAM with Dynamic Bitline Loads" ISSCC89 Digest of Technical Papers pp. 250-251, February 1989): in this method the clamping operation is released for a period during which the data stored in the memory cell 5 is read out to the bit line pair 3 by turning on the word line 9 thereby to efficiently generate a potential difference between the bit line pair 3 and thereafter the clamping operation is started.
In the conventional reading circuit, however, the timing of starting the release of the clamping operation coincides with a time point at which the equalizing operation is ended by controlling the equalizing signal ATD on the first control line 6. So if the word line 9 is turned on to read out the data of the memory cell 5 to the bit line pair 3 at a time point earlier than the time point at which the equalizing operation is ended, the read-out operation is started while remaining the clamping operation unreleased and the potential to be read to the bit line 3 would be necessarily influenced by the effect of the clamping operation as well as that of the equalizing operation. This causes the readout voltage to be suppressed, resulting in difficulties in obtaining stable, high-speed read operations.
Moreover, even with an enough potential difference obtained on the bit line 3 by releasing the clamping operation, if the timing of turning on the subsequent amplifier 4 is delayed, the clamping operation might start before starting the reading operation so that the obtained potential difference would be made smaller before turning on the amplifier 4, leading to a difficulty in obtaining a stable read operation.
Yet further, the input of the differential amplifier 4 in the first stage is obtained only by the potential difference that develops to the bit line pair 3 only by reading out the data stored in the memory cell 5, and therefore the resulting amplification speed of this potential difference is of low level, and the amplification speed of the output of the amplifier 4 also becomes slow. Thus, to implement a further high-speed read operation, it is necessary to connect a positive-feedback type amplifier to the input of the differential amplifier 4. However, in the arrangement in which the bit line 3 is connected to the input of the differential amplifier 4, such an added positive-feedback type amplifier involves so heavy a load that a high-speed amplification cannot be obtained and moreover it results in an increased current consumption.